User:DanClemmensen/old

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Hi! I am an FPGA newbie. I started playing with JOP in December 2007, with no prior FPGA experience. I worked on my project for about four months, off and on, and then had a series of minor setbacks that discouraged me, so I more or less abandoned the project. The setbacks, in order of occurance, were:

  • could not get a DDR controller to work
  • A failed Linux SW upgrade
  • A HW failure that killed my main computer.

I restarted the project in 2009-09, after about 18 months. I recovered my data from the old hard disk and got my development environment set up on my new computer. With a few hours' work over the course of a week, as of 2009-09-12, I am back to where I was in 2008-04, but with some encouraging new information. I have not yet upgraded my project to the latest JOP sources.

This is just a fun hobby for me, with no deadlines.

  • Current Development machine: Intel Core i7 running 64-bit Gentoo Linux,
  • Target: Spartan 3E starter kit.
  • Tools: Xilinx WebPack 11.1, GHDL, GTKWave.
  • Goals: Run JOP on this board. Eventually, use the board to control a homebrew Scanning Tunnelling Microscope.

I decided to use Xilinx rather than Altera because Xilinx has no-cost tools for Linux, while Altera (apparently) does not. My initial problem was that the free Xilinx tool, Webpack, does not officially run on any Linux except RHEL. I spent a long time getting it to run on Gentoo. I documented the result on the Gentoo Wiki. After I restarted the project, I also re-wrote the HOWTO to update it, since Xilinx changes things with each release. The changes are mostly for the better.


I adapted the JOP project for the old Spartan 3 starter kit to work on my (quite different) target. As of 2008-02-28, I have made some progress. I fixed up the BRAM initializers and re-structured the VHDL a bit. I can now run JOP in simulation using GHDL and GTKview, and I can run various versions of "blink" on the actual hardware.

I am moving the bootloader from microcode to bytecode, using a method pre-loaded into the method cache as part of the FPGA image. I intend to use various test versions of this bootloader as test drivers for the DDR SDRAM integration. This approach reduces the microcode to less than 1024 words, which simplifies the system. As of 2009-09-12, I have successfully run a test version of the bootloader that reads the Platform flash and displays on the LCD, with breakpoints controlled by the switches.I have not yet integrated the DDR SDRAM.

The bootloader is written in a java subset. I wrote a tool, ExtractBoot, to post-process the boot bytecode to adapt it for this purpose.

I intend to bootload from the platform flash. The platform flash, an xcf04s, is 512KB, and only 280KB is used for the FPGA image. The rest is available for use and can be downloaded together with the FPGA image via the USB cable. It is accessible with a modest amount of effort from the bootloader method. It should take less than 0.2 seconds to complete the load.

I intend to release all of my work under GPLv3/LGPL, as appropriate, but I need a place to put it, and I need some help with structuring the files. My approach differs from the "standard" JOP, and each difference has effects on the code. For now, I am placing all of my changes in a new subdirectory named jop/xininx/s3Esk/, but some of my changes should be at higher levels.

  • I use Make, but JOP mostly uses ant
  • I use Linux, JOP mostly uses Windows
  • I use Spartan 3, JOP mostly uses Cyclone

Within the Spartan world:

  • JOP uses the Spartan 3 starter kit, I use the (very different) Spartan 3E starter kit
  • JOP uses the full-up Xilinx ISE, I use WebPack
  • JOP uses ModelSIM, I use GHDL and GTKWave

Within the Xilinx ISE/Webpack toolchain on Linux:

  • Xilinx supports only RedHat Enterprise Linux (RHEL). I use Gentoo Linux.
  • Most Xilinix users use the ISE GUI. I use the Xilinx tools in batch mode.
  • WebPack is restricted to 32-bit Linux. I use 64-bit Linux.

I have what I believe to be good reasons for each of my choices, but the result is that my development system and file layout are very different from the standard JOP.

Please look at my early logs:

if you are interested in the details of my progress.

Please look at User:DanClemmensen/Current for my current activities.

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