User:DanClemmensen/Archive 2007-12
From JopWiki
NOTE: this is page is a copy of my log, crudely wikified from my original HTML document. The format is therefore crude. the document was originally a note from me to myself, and is therefore not very coherent. This page os a log of my efforts from 2007-12 up until 2008-02-22, and may be interesting for developers who are just starting with the Spartan 3E board. For my more recent efforts, please see User:DanClemmensen/Archive 2008-02-22
Contents |
[edit] JOP Project
The Java Optimized Processor is a soft-core implementation of a JVM. It has been implemented on multiple FPGAs, including both Altera and Xilinx. JOP runs at 100Mhz on the Cyclone I and executes most bytecodes in a single cycle. Its performance is about 100 times better than TINI and perhaps ten times slower than compiled Java on a modern CORE 2. JOP occupies less than 2,000 LCs on an Altera Cyclone. A Cyclone 3C5 costs about $15.00 and has 5,000 LCs. A system consisting of a single FPGA and a very small number of additional chips can be used as a powerful embedded controller. JOP VHDL and Java code is available and is free for non-commercial use.
To implement JOP, I will need an FPGA evaluation board and FPGA development software in addition to the JOP software and FPGA sources. Xilinx and Altera both make their software available at no cost, but in binary form only. It is not obvious how to run the Altera software on Linux, Xilinx software at least tries to run on Linux. I will therefore experiment with Xilinx first.
[edit] Xilinx ISE
I downloaded the Linux version of the WebPACK installer, and ran it. This took awhile. Meanwhile, I found many sites on the web that describe the installation and use of ISE on non-RHEL, including HOWTO Xilinx at the Gentoo wiki. In addition, the Xilinx installer warned against trying to install the USB driver and recommended downloading the source and building for my distro.
I finally managed to get the WebPack ISE fully installed (see log below), and I worked through the tutorial. Unfortunately, the tutorial is for a different board, so I cannot test the result.
[edit] Learn to use the board
I have not found a step-by-step procedure for learning to use the Spartan 3E Starter kit, so I will try to derive one. My first goal will be to rebuild the sample program that is installed on the board, but with a one-character change to the displayed message so that I can tell that I succeeded. I found the reference designs the Xilinx site. I downloaded the s3Esk_startup reference design and the Picoblaze starter which it uses. The startup is well documented, but I will need to run an assembler to generate an HDL file from the assembler source file. Neither the assembler nor the generated HDL file are provided with the startup. The Xilinx assembler is (of course) Windows-only. I found and installed picoasm. This is a simple command-line program that is derived from the assembler in the kpicosim IDE. I do not want to install the full IDE since I do not intend to use PicoBlaze much. I did post questions on the Xilinx devel board forum.
[edit] Picoasm
I have no documentation for picoasm other than the ./picoasm -h output. With this, I assembled control.psm to create control.vhd, and compared the result to the control.vhd supplied in the startup design. They differ: the delivered file is a dual-port RAM, while the assembled file is a single-port RAM. It is fairly clear that the difference is from the "template." I will search for picoasm templates, and if I cannot find the right one, I will back-derive the template from the supplied control.vhd.
A google search for "kcpsm3 dual port ROM_form.vhd" found it at Koders. I was not aware of Koders, but it seems to have a fair amount of picoblaze stuff.
I was able to build the control.vfd, and use it to build the fpga .bit file. I downloaded it to the board and it worked.
[edit] DDR SDRAM
The startup design does not use the RAM, and there are many indications on the net that using the RAM on this board is hard. I finally found a forum where this had been resolved: a developer had modified the Opencores DDR core for this board and the result is available at this web site. Even better, he provides code for simple standalone RAM test for the board. I now need to figure out how to build his code.
The makefile uses ghdl for simulation and GTKWave to display the result. These open source tools should permit large-scale behavioral simulations that the no-cost version of the Xilinx XST lite refuses to do.
I emerged ghdl and gtkwave and analyzed the makefile: It assumes that you already have a shared location for the UNISIM binaries. Unisim is a set of VHDL libraries supplied in source form by Xilinx with the ISE. It apparently includes behavioral simulators for a massive collection of external devices. Apparently, when you choose a behavioral modeling package, you are supposed to compile unisim using that package and make the result available in a shared directory. I compiled with ghdl, found errors, found a forum posting, and fixed the errors.
ISE Tasks:
| Task | status | date |
| purchase the Xilinx development board | opened | 2007-12-25 |
| download and install the Xilinx tools. | done | 2007-12-26 |
| install Xup | done | 2007-12-26 |
| download Xilinx starter kit reference design | done | 2007-12-26 |
| test Xup | done | 2007-12-26 |
| install usb-driver environment | done | 2007-12-27 |
| create the development environment | done | 2007-12-26 |
| build the FPGA image | done | 2007-12-29 |
| write picoblaze "hello, world" | done | 2007-12-29 |
| run "hello, world" in simulation | ||
| run "hello, world" on the board | done | 2007-12-29 |
| put "hello, world" in the flash and run it. | done | 2007-12-29 |
[edit] New Tasks
After a considerable effort, I got the WebPack ISE installed. Two days later, it quit working after an emerge world: I think the problem involved glibc, but I'm not sure. I then resolved to try to minimize the dependency of my development environment on such problems. As it happens, the makefile in David Ashley's DDR project uses an interesting approach, so I intend try to document it and use it. Basically, the ISE is a GUI front-end that invokes several batch-mode applications. David's makefile runs these batch applications directly. It seems that the applications are more robust (i.e., they have fewer dependencies on the system environment) when they are run in this mode. In addition, the script uses ghdl and GTKWave for the VHDL verification and simulation steps rather than using the Xilinx sim lite or ModelSIM. David's script also uses xs3prog instead of iMPACT. After some work I was able to use these techniques to simulate, build, and download the application. I now intend to automate this approach.
In addition to the advantages in flexibility and robustness, ghdl is unrestricted with respect to the size of the simulaton, and GTKWave is unrestricted in the number of displayed signals.
[edit] Using David's approach
First, I created a local "standard directory" for ghdl at /opt/ghdl/lib, and added the ghdl version of the xilinx unisim to it. I then re-worked the Makefile to strip out the unused stuff and the stuff that is now in the /opt/ghdl makefile.
Further analysis shows that the Xilinx tools are driven from main.prj, which was supplied as a source in the ddr tarball: let's make that from the makefile instead. It's a textfile listing the vhd files, one per line, so we can emit it.
David's scripts use several Xilinx apps in batch mode, but they replace IMPACT with xs3prog. Since I have already "tamed" IMPACT by wrapping it with libusb, I will change the script to use IMPACT in batch mode. Xilinx has documented IMPACT batch mode here.
[edit] GTKWave signals
I ran "fast_blink" in simulation. Now I want to analyze the results. I brought up GTKWave, but I con't understand how to find signals.
- study the fast_blink and JOP definitions
- read the GTKWave manual
OK, I found the problem and fixed it: fast_blink.asm was using some obsolete opcodes, which silenty get changed to NOPs. Thus, the WD signal was not being toggled.
[edit] Initializing Xilinx memory blocks
Xilinx Spartan 3 devices have 16Kb (2KB) memory blocks. To convince the synthesis tools to use these blocks, you apparently refer to specifically-named entities that are defined in the Xilinx UNISIM. (These names are probably also hard-coded in the Xilinx synthesis application.) For picoblaze/picoasm, the names are part of the template files. For JOP, the names are somehow generated by the "Blockgen" application.
The picoasm scheme is more flexible, so I intend to modify Blockgen to use the picoasm templates. This is particularly important since I think we can modify the JOPM microcode to use a single 1024x18. The idea is to use an 18-bit instruction set to replace the current 8+2 bit set. The extra 6 bits can be immediately used to extend the "immediate" range from 2^^5 (32) to 2^^12 (4096) removing the need for the jump table. The 18-bit instruction can also (probably) decrease the need for decode logic, and we can eliminate the offset table by being slightly clever.
Approach:
- modify Blockgen to use templates.
- change the makefiles/bat files to use the new blockgen.
- understand the mapping from word values to Xilinx RAM encoding.
Using picoblaze, startup, and control.vhd as a worked example, I can probably create a rom_JOPs3E.vhd template and a blockgen to populate it. If picoblaze and JOPM are similar, then we populate an instance of a Xilinx RAMB16_S9_S18 with a set of attributes named INIT_00 through INIT_3F, each a string of 64 hex nybbles. This is 1024 16-bit words. the word at address 0 is the rightmost word in INIT_00. The rightmost bit of the word in address 0 is the rightmost bit in INIT_00. Bits 16 and 17 of each word are stored in the "parity bits." The parity bits are initialized via attributes INITP_00 through INITP_07. Each is a 64-nybble string. The rightmost two bits of INITP_00 are the two parity bits (17and 16) of the word with address 0. The rightmost bit is bit 16. If JOPM uses a different bit order from Picoblaze, then blockgen (or rom_JOPs3E.vhd) will need to adjust.
- analyze blockgen
- adapt to emit a RAMB16_S9_S18
- analyze xram.vhd, create rom_JOPs3E.vhd
[edit] RUN "Blink" on the FPGA
This requires that we create a simple JOP project for the s3Esk. "Simple" means no external memory.
| copy s3sk project to a new directory | (jop/xilinx/blink_s3Esk) | done |
| create a makefile | prelim is done | |
| strip out the external memory | done | |
| figure out how to build the internal memories for Xilinx --identify internal mem files: | jtbl.vfd offtbl.vhd |
|
| build in simulation | ||
| run in simulation(?) | ||
| build for FPGA | ||
| run | 2008-02-10 |
[edit] PF-load and HID
OK, Finally we have Blink running on the board. We will now to build a minimal HID peripheral and a minimal Platform-flash peripheral. "Minimal" means bit-banged: basically, have a way to read and write all the relevant data and control bits, and then do everything else in JOPM language.
First, we now have worked examples with blink. Each individual IO device has a sc_*.vhd file, and all IO devices for a JOPM system are components of one "configuration" defined in the one scio_*.vhd file. Our particular JOPM, blink, uses scio_min.vhd.
To build a minimal HID, we will add sc_hid.vhd, and then add the
scio_hid component to scio_s3Esk.vhd. We derive sc_hid.vhd from
sc_test.vhd, and scio_s3Esk.vhd from scio_min.vhd.
| Task | status | date |
| study scio and sc | done will copy scio_min.vhd to scio_s3Esk.vhd | 2008-02-11 |
| write scio_s3Esk.vhd | done | 2008-02-11 |
| write sc_s3Esk_hid.vhd | done. adapted sc_test_slave.vhd | 2008-02-11 |
| write sc_s3Esk_spi.vhd | done. adapted sc_s3Esk_hid.vhd | 2008-02-11 |
| modify jop_s3Esk.vhd | done | 2008-02-11 |
| modify tb_s3Esk_jop.vhd | done | 2008-02-11 |
| modify makefile | done | 2008-02-11 |
| compile in ghdl | done | 2008-02-12 |
| run in ghdl | ||
| modify main.ucf | ||
| write pf_test.asm | ||
| build for target |
Development environment tasks:
| Task | status | date |
| Design an approach | started | 2008-01-09 |
| create an "install script" for the GHDL version of the unisim library | ||
| install the library | ||
| create an "install script" for the Xilinx batch tools | ||
| "install" the Xilinx batch tools | done | 2008-01-09 |
| create the generic makefile (?) | ||
| convert the DDR project to use the generic approach (as a test) | ||
| rebuild the DDR project "from scratch" with the new approach | ||
| add HID driver and make sure the DDR tester halts on error | ||
| create Eclipse wrapper(?) |
We "install" the batch tools by creating a wrapper script named "xilinx" in /use/local/bin. This script is simply the xilinx setup script modified to run any xilinx command, by adding
- export LD_PRELOAD=/opt/usb-driver/libusb-driver.so
- ${XILINX}/bin/${PLATFORM}/$@
at the bottom. now, if you type
- xilinx ise
the script runs the ISE, and if you type
- xilinx impact foo
the script runs impact with a parameter of foo.
After deciding to create the new development environment, the JOP part of the project becomes:
| Task | status | date |
| download the JOP | downloaded. | 2007-12-01 |
| create the Jop project | 2007-12-30 | |
| describe the board (ucf file) | 2007-12-30 | |
| add Jop vhds to project | ||
| remove DDR test driver | ||
| run JOP in simulation | ||
| build the FPGA image | ||
| write "hello, world" | ||
| run "hello, world" in simulation | ||
| download JOP on the board |
[edit] JOP Unit Testbenches
goal: find and fix problems with GHDL simulation, since the big-bang approach failed. My JOP directory structure starts in "Jop Project". I did a CVS checkout , which created "Jop Project"/jop. this directory includes ./jop/vhdl as a subdirectory structure. I added a paralled subdirectory structure ./jop/tb, in which I intend to create a unit-test tb file for each interesting file in the vhdl tree. My preliminary intention is that the tb directory will contain only source files. I also added a directory ./jop/test in which to actually build and run the unit tests. The critical file is ./jop/Makefile. So far, I have created a total of one tb.
[edit] JSTM Architecture
The JSTM is an STM controller based on JOP and running on a Spartan 3E starter kit. The interface to the STM hardware will be via the ADCs and DACs on the board and on some digital signals to drive the stepper motor for coarse positioning. The interface to the rest of the world is via TCP/IP over ethernet.
To support this, we will first get a standalone minimal JOP running. We will then add additional modules until we have a full-up JOP system. Finally we will add the STM.
Module order:
- HID peripheral
- JOP core (no mem)
- flash
- RAM
- Ethernet
- STM
If the ethernet is too hard to implement, we will revert to USB, but this is a multi-step process because it means switching to Xup. If we switch to Xup, we will first need a Xup flash programmer (or something) to permit easy switching of USB between programming and normal use.
[edit] JOP core and HID
It is difficult to test the JOP core and HID separately, so I will
first study the JOP core again and then design the HID by example from
other JOP peripherals and from the Xilinx startup reference design.
Analyze the Spartan 3 project file list to decide what files I need. These files are used in the Spartan 3 project:
| File | purpose | disp |
| top\jop_config_xs3.vhd | ? | |
| vhdl\core\jop_types.vhd | package type definitions. Apparently, a set of standard signal names? | keep |
| vhdl\simpcon\sc_pack.vhd | package for SimpCon definitions. Apparently, a set of standard SimpCon signal names? | keep |
| vhdl\scio\fifo.vhd | define a FIFO IO device. used in sc_uart.vfd? | |
| vhdl\scio\sc_uart.vhd | UART. SimpCon. | |
| vhdl\scio\sc_sys.vhd | counter/timer, timer interupt, wd, and general interrupt handler. SimpCon. | keep |
| vhdl\scio\scio_min.vhd | minimal IO suite. ctr, wd. SimpCon. Used for code cownload? | keep |
| vhdl\core\extension.vhd | core's interface to memory, multiplier and IO MUX for din from stack | keep |
| vhdl\core\bcfetch.vhd | bytecode fetch and address translation | keep |
| vhdl\core\fetch.vhd | instruction fetch and branch (formerly included bcfetch) | keep |
| vhdl\core\shift.vhd | barrel shifter | keep |
| vhdl\core\cache.vhd | Bytecode caching (method cache?) | keep |
| vhdl\xilinx\xs3_jbc.vhd | bytecode memory/cache for JOP( Version for Xilinx Spartan-3) | keep (modify?) |
| vhdl\memory\mem_sc.vhd | External memory interface with SimpCon. Translates between JOP/extension memory interface and SimpCon memory interface. |
keep |
| vhdl\memory\sc_sram32.vhd | SimpCon compliant external memory interface for 32-bit SRAM (e.g. Cyclone board, Spartan-3 Starter Kit) | replace with DDR16 |
| vhdl\core\stack.vhd | Stack/Alu | keep |
| vhdl\core\mul.vhd | booth multiplier (32x32 serial) | keep |
| vhdl\core\core.vhd | cpu core, stack, pc connections (executes microcode?) | keep |
| vhdl\core\decode.vhd | microcode decoder. generate control for pc and stack | keep |
| vhdl\jtbl.vhd | (generated by jopa. bytecodes implemented in bytecode?) | |
| vhdl\offtbl.vhd | (generated by jopa. jumptable for jtbl.vfd?) | |
| vhdl\rom.vhd | ||
| vhdl\xilinx\xram.vhd | internal memory for JOP3 modified for Xilinx ISE to use Block SelectRAM+ | keep (modify?) |
| vhdl\xram_block.vhd | ||
| vhdl\core\jopcpu.vhd | The JOP CPU. (apparently a wrapper for several of the other core files.) | keep |
| vhdl\top\jop_xs3.vhd | top level for Spartan-3 Starter Kit | keep (modify) |
[edit] STM
- define off-board interface.
- design off-board STM circuit.
- build off-board STM circuit and connectors.
- create the FPGA drivers for the STM.
- wire up the STM
- write the JAVA to run the STM and send frames to Linux
- design a custom STM board to replace the devel board
[edit] Log
| Date | Activity |
| 2007-11-20 | began investigating JOP |
| 2007-12-01 | downloaded JOP and Xilinx ISE |
| 2007-12-01 | installed ISE, encountered problems |
| 2007-12-02 | worked a bit on the problems |
| 2007-12-08 | researched ISE problems, found hint on the Gentoo HOWTO Xilinx talk page: ISE is not compatible with tcl-8.4.15, must downgrade to tcl-8.4.14. |
| 2007-12-09 | decided to upgrade Linux, screwed up Nvidia driver |
| 2007-12-11 | researched Nvidia issue, recovered as follows:
|
| 2007-12-12 | downgraded tcl:
|
| 2007-12-12 | board arrived. Wrong board: Startan 3, not Spartan 3E(my fault.) I had ordered a Spartan3 board, not a Spartan3E board. The 3 eval board is same cost, but greatly inferior features. Ordered new board, requested RMA for old board. |
| 2007-12-12 | fixed help problem by:
fixed root's problems by:
began working through tutorial
window closed unexpectedly several times. turned off compiz: this solved the problem. Not specific to ISE. |
| 2007-12-21 | Spartan 3E board arrived. |
| 2007-12-24 | finally found a one-sentence description of the ISE-simulator problem: ISE has this (and other?) problems when running on a system with glibc>=2.5. There is no documented way to downgrade a modern Gentoo. The recommended workaround is to download the 2006.1 stage3 install tarball, expand it, and chroot into the resulting directory: this gives you a consistent environment with glibc<2.5. |
| 2007-12-25 | Opened the box and turned on the board. Yea! I went to the gentoo mirror site and navigated to: and then downloaded but I could not make it work. |
| 2007-12-26 | further web search found the Electronic Design Automation page on the Gentoo wiki, which recommends a solution to glibc problems and points to an expert explanation, which has a better solution. I chose to recomplile glibc with the backward-compatability option. I added
to
After a fairly long emerge, I re-ran the sim. It worked!. emerged sdcc (tool needed to compile part of Xup (specifically, the code for the on-board 8051 on the USB slave on the Spartan3E board.) Downloaded Xup and built it. tried to read Xilinx DVD and failed. eventually read DVDs on my Windows laptop, desperately looking for info on the starter kit itself. Finally found a link to the Xilinx 3estarter, and followed it to the reference designs. Downloaded the s3esk_startup reference design and the picoblaze starter which it uses. tried to use xup to download the (precompiled) s3esk_startup.bit file: failed initially, but eventually discovered some stuff:
were not in the file. I added:
|
| 2007-12-27 | Discovered the third alternative way to download: "wrap" ISE with the usb-driver library. This info was referenced in the HOWTO, but the structure of the HOWTO made it hard to identify.
Created a login on the Gentoo wiki and re-wrote the HOWTO. Downloaded usb-driver source. read the README emerge fxload #tool will be needed later emerge libusb #userspace USB lib. follow the instructions in the README. The part about using fxload is obscure but necessary. Finally got it running! Added more to the HOWTO. Began researching the startup project decided I needed an assembler-- downloaded picoasm, untar and build. |
| 2007-12-28 | no documentation for picoasm, ./picoasm -h is probably enough.
|
| 2007-12-29 | searched web, found a dual-port rom form, downloaded, re-ran assembler. compare equal.
modified the source to display "Hello, World!", re-assembled, used ISE to rebuild FPGA image, downloaded. It worked! Yeah! Learned how to program the PROM. Instructions are in the Spartan3E starter kit manual. |
| 2007-12-30 | began studying JOP and planning. wrote plan
downloaded the new JOP reference handbook, began working through it. tried to make the tools. failed. |
| 2007-12-31 | Joined the JOP forum on Yahoo described the make failure. Isolated the make problem: makefile uses semicolons instead of colons as classpath separator. Replaced semicolons with colons: the tools then built. With a bit of free interpretation, all of the non-ISE portion of the JOP builds. The ISE portion cannot work in any event since there is no target for the Spartan 3E starter kit. re-read the JOP reference guide. |
| 2008-01-01 | Began analysis of .vfd files in the Spartan3 JOP build, to convert to Spartan3E. |
| 2008-01-05 | Found a DDR SDRAM core already adapted for my board. |
| 2008-01-07 | Arrgh! after an emerge, ISE again fails. We are now using glibc-2.6, which does not have backward compatability. 2.5 and 2.7 do have it. |
| 2008-01-08 | Emerged gtkwave and ghdl (ghdl was a struggle, since it needs gnat, which is masked.) I want to move away from the ISE GUI and just
use the Xilinx batch programs. Began working through the ddr make. ghdl found errors in unisim. Found a forum thread that shows how to correct the errors. |
| 2008-01-09 | built and downloaded the DDR test to the starter board. It seems to work. Began researching the HID interface. |
| 2008-01-11 | began new document for HID. decided on SimpCon to allow later use in JOP |
| 2008-01-12 | began learning VHDL. randomly grabbed this tutorial from the dozens that showed up on a google search for "VHDL tutorial." |
| 2008-01-13 | Wrote a cryptic overview of VHDL for experienced software developers.
Found a post here on precompiling and using libraries in GHDL created a common ghdl library directory. |
| 2008-01-16 | Created the s3Esk subdirectlory and began converting windows-->Linux make and bat added Makefile from oc_ddr proj, adapted for s3Esk |
| 2008-01-17 | Fixed mismatch between tb_jop.vhd and jop_s3sk.vhd, by creating tb_s3Esk_jop.vhd and jop_s3Esk.vhd. GHDL crashes while compiling simulation/bytecode.vhd |
| 2008-01-18 | decided to create unit-test testbenches for each JOP VHD file. and planned the work |
| 2008-01-19 | completed layout of unit test scheme and implemented first tb. |
| 2008-01-20 | trying the full compile again. GHDL hates sc_mem.vhd: the instantiation of cmp_cache crashes the compiler. succesfully compiled and ran JOP in sim, but I don't know what to check for next. |
| 2008-01-22 | Researched loading of javacode from the Platform flash: It appears to be fairly straightforward. Platform flash is loadable via USB cable. If is 512KB, fo which <280KB is used to load the FPGA, so we have 225KB free for a Java OS or bootloader. |
| 2008-01-23 | try to run "blink" in simulation: tidied up directories, created a "ghdl" directory similar to "modelsim", created makefile, built and ran sim |
| 2008-01-25 | built a blink in simulation and ran it. Tried to figure out the result... Make system needs a major re-work |
| 2008-01-26 | studied GTKWave and JOP architecture. noticed a descrepancy in mem_rom.dat |
| 2008-01-27 | fast_blink.asm included obsolete opcodes. fixed. fast_blink now runs in sim. |
| 2008-02-01 | began studying Xilinx memory blocks |
| 2008-02-02 | created XBlockGen to replace Blockgen. |
| 2008-02-03 | wrote s3Erom.vhd and ROM_1024x18_vhd.template, and successfully generated rom_block.vhd |
| 2008-02-05 | compiled and ran s3Esk in simulation.
began compiling for target. need to correct the ucf file for my target |
| 2008-02-10 | successfully compiled for target, with a non-functional DDR system, and successfully ran the blink test on the target. |
[edit] JOPM Optimization
The JOP miocrocode uses a 10-bit word. The Spartan 3E FPGA uses a BRAM with a hardware size of 1,2,4,8,9,16,18,32,or 36 bits. The 10-bit word is just about the worst possible size.
Of the ten bits, two of the bits are dedicated: nxt and opd. These bits have several interesting charactreistics: they are never both set at the same time, and neither bit is set for a BZ or BNZ
On a different note, we can add 8 bits to every instruction. If we can get the pipeline to not stall, we use the bits as branch bits. By allocating location 0 as "nxt" we get one more bit. This should let us eliminate both the offtbl and the jtbl.
To eliminate the jtbl, Java byteodes will immediately jump to their own offsets (0-255) in the JOPM. each instruction will have a "next" addr, which is either zero or the next relative instruction. the next relative instruction is either in the next page or the previous page, where a "page" is 256 instruction words: there are a total of 4 pages of microcode (1024 instructions.) A bz/bnz is different: it branches to any pair of locations. The instruction branches to the even word if the pair of the condition is zero and to the odd location if the condition is non-zero. This means that the current 64 branch instructions are reduced to 1 , and we have 63 extra instructions to use. If this reduces the instruction count below 128, we may recover an additional bit, which extends the jump address to ten bits and removes the restriction.
[edit] Bytecode Bootloader
I removed the bootloader from the JOPM to reduce the number of words to below 1024. I must now add a bootloader somewhere, either as a separate VHDL state machine or in bytecode. Bytecode is "free" on the Spartan 3E, because the amount of program flash used for the FPGA is fixed no matter what the FPGA configuration is. therefore, we can initialize the method cache BRAM at no cost. We place a boot loader in the method cache, but we will probably need a very small init sequence in the JOPM as well, to get the stack and jpc set up.
The Boot loader must be written in "jbc--": the subset of the java bytecodes that is impleneted in the JOPM. Bytecodes that are themselves implemented in Java cannot be used. We therefore need an assembler for this language. The standard jbc assembler is Jasmin, which emits a classfile. Our alternatives are to either write a really primitive assembler, or use Jasmin and write a really primitive classfile decoder. We can use XBlockGen to create the initialized method cache in either case.
Analysis of the existing boot loader shows that it performs the following steps:
- stack pointer <=stack_init
- if CPU 0:
- moncnt <=1
- load word 0, word 1, and data into RAM
- word 0 is length of load
- word 1 is method pointer
- remaining words are data, not analyzed by loader
- heap<= word 0
- mp <= word 1
- jjp<= (mp+1)
- jjhp<=(mp+2)
- invoke mp
We still need to analyze how to cause the JOPM to execute a method that is pre-loaded into the method cache. Basically, we need to execute a "nxt" with the jpc pointing to the correct bytecode?
Write a "hello world" program in jbc-- and run it!
