User:DanClemmensen
From JopWiki
Hi! I am an FPGA newbie. I started playing with JOP in December 2007, with no prior FPGA experience.
This is just a fun hobby for me.
- Development machine: Intel Core2 Duo running Gentoo Linux (x86, not AMD64)
- Target: Spartan 3E starter kit.
- Tools: Xilinx WebPack 9.2i, GHDL, GTKWave.
- Goals: Run JOP on this board. Eventually, use the board to control a homebrew Scanning Tunnelling Microscope.
I decided to use Xilinx rather than Altera because Xilinx has no-cost tools for Linux, while Altera (apparently) does not. My initial problem was that the free Xilinx tool, Webpack, does not officially run on any Linux except RHEL. I spent a long time getting it to run on Gentoo. I documented the result on the Gentoo Wiki[1], where I am Arch_dude.
The next problem was the lack of a DDR SDRAM driver for the Spartan 3E starter kit. I finally found a worked example of this driver. I got it running, but I have not yet integrated it.
I then began adapting the JOP project for the old Spartan 3 starter kit to work on my (quite different) target. As of 2008-02-28, I have made some progress. I fixed up the BRAM initializers and re-structured the VHDL a bit. I can now run JOP in simulation using GHDL and GTKview, and I can run various versions of "blink" on the actual hardware.
I am moving the bootloader from microcode to bytecode, using a method pre-loaded into the method cache as part of the FPGA image. I intend to use various test versions of this bootloader as test drivers for the DDR SDRAM integration. This approach reduces the microcode to less than 1024 words, which simplifies the system. As of 2008-03-07, I have successfully run a test version of the bootloader that reads the Platform flash and displays on the LCD. I have not yet integrated the DDR SDRAM.
I intend to bootload from the platform flash. The platform flash, an xcf04s, is 512KB, and only 280KB is used for the FPGA image. The rest is available for use and can be downloaded together with the FPGA image via the USB cable. It is accessible with a modest amount of effort from the bootloader method. It should take less than 0.2 seconds to complete the load.
I intend to release all of my work under GPLv3/LGPL, as appropriate, but I need a place to put it, and I need some help with structuring the files. My approach differs from the "standard' JOP, and each difference has effects on the code. For now, I am placing all of my changes in a new subdirectory named jop/xininx/s3Esk/, but some of my changes should be at higher levels.
- I use Make, but JOP mostly uses ant
- I use Linux, JOP mostly uses Windows
- I use Spartan 3, JOP mostly uses Cyclone
Within the Spartan world:
- JOP uses the Spartan 3 starter kit, I use the (very different) Spartan 3E starter kit
- JOP uses the full-up Xilinx ISE, I use WebPack
- JOP uses ModelSIM, I use GHDL and GTKWave
Within the Xilinx ISE/Webpack toolchain on Linux:
- Xilinx supports only RedHat Enterprise Linux (RHEL). I use Gentoo Linux.
- Most Xilinix users use the ISE GUI. I use the Xilinx tools in batch mode.
I have what I believe to be good reasons for each of my choices, but the result is that my development system and file layout are very different from the standard JOP.
Please look at my early logs:
if you are interested in the details of my progress.
Please look at User:DanClemmensen/Current for my current activities.
