Projects
From JopWiki
JOP is used in academic and industrial projects. Feel free to add a short description of your project and a link and/or reference to a published paper.
Contents |
[edit] Academic
[edit] PhD Theses
[edit] Time-Predictable Java Chip-Multiprocessor
This project proposes a multiprocessor architecture consisting of JOP (Java Optimized Processor) cores and a shared global memory. The design of a communication and synchronization facility for controlling the CPUs and the access to the shared memory is one of the scientific goals. Furthermore the definition of a scheduling system that is capable to distribute the threads of a real-time application among the processors describes another technical challenge. The solution is designed to be time-predictable with a known, tight upper bound of the WCET (worst-case execution time) of each individual task. The major goal is the implementation in a low-cost field-programmable gate array (FPGA).
- Christof Pitter. Time-Predictable Java Chip-Multiprocessor. PhD thesis, Vienna University of Technology, Austria, 2009. pdf
[edit] Interactive WCET Analysis
Clepsydra is a static WCET analysis tool for Java programs. Written in pure Java and 100% open-source, it is designed to work with JOP by default. You can find the source code, a manual, and the API documentation for Clepsydra by visiting the Volta project home page.
- Trevor Harmon. Interactive Worst-case Execution Time Analysis of Hard Real-time Systems. PhD thesis, University of California, Irvine, 2009. pdf
[edit] Agent Computing Platform for Distributed Satellite Systems
An Agent Computing Platform is defined as the hardware and software layers used to implement a real-time embedded agent middleware. In this case, JOP is added to Gaisler's GRLIB as an AHB Master with an APB Slave as a Java based networking co-processor and a research platform to test new fault-tolerant Java-based agent middleware.
Online Publications & Final Thesis copy to come soon...
- Christopher P. Bridges and Tanya Vladimirova. Dual Core System-on-a-Chip Design to Support Inter-Satellite Communications NASA/ESA Conference on Adaptive Hardware and Systems (AHS '08), 2008. pdf
- Christopher P. Bridges, c.p.bridges@surrey.ac.uk
[edit] Master's Theses
[edit] JopSpeech SDK
The JopSpeech SDK is a speech recognition Software Development Kit (SDK) developed for the Java Optimized Processor (JOP).
The SDKs consist of a set of software components, interfaces and hardware for audio in and out - the purpose of JopSpeech is to allow developers and researchers to take advantage of speech technology in the embedded Java infra-structure of JOP. JopSpeech SDK contains a set of components to build speech models, algorithms like the Fast Fourier Transformation (FFT), the Mel Frequency Cepstral Coefficients (MFCC), Linear Predictive Coding (LPC), Dynamic Time Warping (DTW) and K-near are implemented. A hardware extension to the BaseIO board is also included, enabling JOP to interface with microphones and loudspeakers. JopSpeech also proposes an architectural model built on the "Pattern Recognition Approach" proposed by L. Rabiner and B.H. Juang as a part of its architecture for developing and testing speech recognition systems. The SDK has been used to build models tested on both a speaker-dependent and a semi-speaker-independent system with a prediction error of 96,7% JopSpeech SDK has been developed by Jens Kristian Rasmussen and Mikael Lundsgaard in collaboration with Martin Schoeberl and Rasmus Pedersen.
- Jens Kristian Rasmussen and Mikael Lundsgaard, JOPSPEECH Embedded Java Speech Recognition SDK. Master's thesis, Copenhagen Business School, Denmark, 2007. pdf
[edit] Bluetooth API
JOP is now able to communicate with Bluetooth devices, such as mobile phones etc. The blueonjop.sourceforge.net project is an implementation of the Java Specification Request 82, which standidize a set of Java APIs to allow Java-enabled devices to integrate into a Bluetooth environment. To Bluetooth enable JOP, you need the API that can be downloaded from the project website, and a Bluetooth Intelligent Serial Module that connects to JOP through the RS-232 port. The project website, and the available thesis describes the component and the intermedidiate API implementation. To view a quick example on how to push a file to a mobile phone throught the OBEX Push Profile browse to the example section at the website.
- Kasper Hansen, Bluetooth API for JOP. Master's thesis, Copenhagen Business School, Denmark, 2007.
[edit] WCET Analyis
In this thesis, we discuss the WCET analysis of real-time Java applications, and present a tool analyzing task executed on the Java Optimized Processor (JOP). JOP is an implementation of the Java Virtual Machine in hardware, and uses a cache fetching all instructions of a method at once, which needs to be taken into account. Two techniques for calculating a WCET bound have been implemented, the Implicit Path Enumeration Technique (IPET), translating the calculation to a maximum cost circulation problem, and a dynamic approach using the timed automata model checker Uppaal.
- Benedikt Huber. Worst-Case Execution Time Analysis for Real-Time Java. Master's thesis, Vienna University of Technology, Austria, 2009. pdf
[edit] Schedulability Analyzer for Real-Time Systems (SARTS)
SARTS is a model-based schedulability analysis tool for hard real-time systems in Java. The applications need to be written for a safety-critical version of Java and the target hardware is JOP.
LEGO Candy Sorting Machine: The candy sorting machine was developed as a use case for the SARTS thesis. The LEGO PCB, LRBJOP, fitted with a JOP processor is used to control a LEGO candy sorting machine. A video of the machine is available on Youtube. This machine was developed in conjunction with a survey report on real-time development in Java. The project report can be found here. The application used to control the machine is also used as a test application in the development of a schedulability analyzer, which translates applications written for JOP into a UPPAAL model, and uses UPPAAL to perform schedulability analysis. The project web site contains links to the video and the final report.
- Thomas Bøgholm, Henrik Kragh-Hansen, and Petur Olsen.Model Based Schedulability Analysis of Real-Time Systems. Master's thesis, Aalborg University, Denmark, 2008. pdf
[edit] Bachelor Thesis
[edit] Lego PCB (LRBJOP)
Lego Mindstorms is a robotics invention system of the Lego Group. It was intended for children, but turned out to be a great toy for adults, too. It combines electric components like sensors and actuators with Lego bricks and Lego Technic parts, such as gears, wheels and axles, to build robots and other automated or interactive systems. The Lego invention systems have a powerful infrastructure which makes it easy to construct various kinds of mechanical and electric systems, like robots. However, Lego Mindstorms originally had very limited program capabilities (e.g. no usage of variables, expressions and function calls in the RCX code). Therefore, a more powerful processor was desirable. In this project, we use Lego Mindstorms sensors and actors, but build our own Printed Circuit Board to use the Java Optimized Processor (JOP) as a central processing unit instead of the Lego RCX. The result is a PCB which provides everything needed to control robots with JOP, and has some additional features to play with, too. See also Lego PCB.
- Alexander Dejaco and Peter Hilber. LRBJOP: A Lego Robot Controller PCB for the Java Optimized Processor. Bachelor's thesis, Vienna University of Technology, Austria, 2007. pdf
[edit] JOPtimizer
Modern Java Virtual Machines (JVM) for desktop and server computers use just-in-time (JIT) compilation to increase their performance. For embedded Java processors, JIT usually is not feasable. Therefore the java bytecode needs to be optimized for a specific platform ahead-of-time. To generate optimized bytecode for the JOP Java processor several existing tools were compared. In order to implement optimizations for embedded Java processors a framework called JOPtimizer was created. Using this framework a method inlining optimization was implemented which honors the restrictions of the target platform.
- Stefan Hepp. Optimizing Java Bytecode for Embedded Systems. Bachelor's thesis, Vienna University of Technology, Austria, 2009. pdf
[edit] Other Projects
[edit] JopVga
The JopVga project presents a hard real-time system consisting of the time predictable Java Optimized Processor (JOP) and a video graphics array (VGA) controller. Both the CPU and the VGA unit share the main memory of the system with the help of a memory arbiter.
[edit] At CBS
- Support vector machine on JOP
- Eclipse Plugin
- WCET analyser (see WCET paper)
[edit] Java Debug Wire Protocol
[edit] SPI SD card interface
Connection of an SD card via an SPI interface. see SD Card
[edit] Industrial Applications
[edit] Kippfahrleitung
Balfour Beatty Austria has developed a Kippfahrleitung to speed up loading and unloading of goods wagons. JOP is used to control up to 15 asynchron motors. This project was the first real system built with JOP and was a great test-case during the developent of the processor. The application (Kfl) is now part of the embedded Java benchmark.
[edit] Telealarm (TAL)
TAL is a remote tele control and data logging system. Communicating via modem or ethernet with a SCADA system or via SMS with a mobile phone. It is in used by EVN. An adapted version of the TAL is in use as a lift controler in a factory.
[edit] Lift
The TAL device is also in industrial usage as a lift controller.
[edit] Railway Communication Device
Another application of JOP is in a communication device with soft real-time properties - Austrian Railways' new security system for single-track lines. Each locomotive is equipped with a GPS receiver, a GPRS modem, and a communication device. JOP is the heart of the communication device in the locomotive.
[edit] The Wizardry Project
The Wizardry Project is an open source network intrusion detection system (NIDS) sponsored by Technica Corporation. Target for the Virtex 4 FPGA platform, this project includes several hardware components that enable basic network intrusion detection functionality:
• The Embedded Protocol Analyzing Classifier (EmPAC) is designed to perform the task of packet classification through protocol analysis. Its goal is to take an unclassified byte stream coming from the Ethernet Physical Layer Interface (PHY) and partition and classify the data blocks into corresponding protocol fields. These include header information such as source and destination address, header and payload sizes, and protocol flags, as well as the payload fields themselves.
• The Enhanced Reconfigurable Content Process (eRCP) is a processor designed as a component of Wizardry to perform the task of inspecting incoming preparsed Ethernet frames for matches to Regular Expressions.
• The Reconfigurable Double Data Rate Synchronous Dynamic Random Access Interface Memory Controller (RDIC) provides each component of Wizardry with priority-based Wishbone compliant access to shared memory resources. Each device may access the shared memory space of other components, along with its own personal private (read and write) and reserved (read only) portions of memory. RDIC supports up to 8 separate Wishbone compliant devices.
• The Java Optimized Processor (JOP) provides an interface to the FPGA. JOP also enables configuration of other components included in Wizardry. This component has write access to the reserved memory space of each component (for configuration data), and has read access to the shared memory space of other components (to retrieve results and output from each component).
• The Web Server provides an interface into the NIDS for the user. As the front end of the Wizardry, the Web Server contains web pages that allow the user of Wizardry to configure modules and view statistics about the state of the FPGA.
The Wizardry Project may be downloaded at http://www.opencores.com/project,the_wizardry_project.
[edit] Toy Applications
[edit] Webserver
Just for fun I implemented a little Web server on JOP. JOP is attached via an ethernet chip with a Linux box and from there to the Internet. The server is now up since March 2003.
[edit] Line Follower
A first start for an FPAG - LEGO Mindstorms interface and the simplest roboter one can think of. An exercise that kids solve in an hour. I needed a little bit longer because I had to solder some components, drill holes, write VHDL code and a few lines of Java ;-)
A small movie: linefollow.mov
[edit] Hobby
[edit] Port JOP to Spartan 3E starter Kit
Xilinx offers an evaluation board called the Spartan 3E starter kit. As of 2008-03-20, this board costs $150.00 USD. The board is considerably more capable than the older "Spartan 3 starter kit," which still costs the same. The only disadvantage of the newer board is The complexity of the RAM interface. Dan Clemmensen is attempting to port JOP to this board as a hobby project. You can track his progress at User:DanClemmensen/Current. The current goal is to Get the DDR memory interface running. Later goals are to get the Ethernet and other peripherals running. Progress is relatively slow since Dan only works on the project evenings and weekends. It appears that a full JOP with DDR will occupy less than 20% of the XCS500E FPGA before any attempt at optimization.
