JopVga
From JopWiki
The JopVga project presents a hard real-time system including a time predictable Java Optimized Processor (JOP) and a video graphics array (VGA) controller. It consists of JOP, a VGA controller, a memory arbiter, a memory interface and an SRAM memory. JOP, the VGA controller, the memory arbiter and the memory interface are implemented on an Altera Cyclone FPGA. The memory interface connects the external memory to the system.
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[edit] The Project
The shared main memory of the system is divided into two segments: 640 KByte are dedicated to JOP and the remaining 384 KByte are associated with the VGA. Both JOP and the VGA controller run at a clock frequency of 80 MHz. The VGA controller uses a VGA resolution of 1024*768 pixels with each pixel consisting of 4 bits. As a consequence the memory used for the VGA display results in 384 KByte (1024*768*0.5 Byte). The horizontal frequency is 60 kHz which results in a horizontal period of about 17 μs per line and 17 ns per pixel. The vertical frequency is 75 Hz. More information concerning the VGA signal timing can be found at:
The memory arbiter implemented for this project is highly configurable. It makes it possible to use several masters that want to access the shared memory. Each master has a different priority. If you want to use it for any other kind of project you can easily change the preferred number of masters you want to use. In addition it is capable of the pipelining read access described in the SimpCon specification.
The sc_arbiter.vhd still has to be tested. Some small test cases can be found in the testbench files called tb_arbiter.vhd and tb_arbiter_3masters.vhd in the folder called simpcon\sim. I haven't had the time to include more testcases so everybody is invited to send me any kind of test files you create. I would appreciate any kind of feedback regarding problems that may occur.
All the necessary files are already checked in CVS. The top-level project file is called cycvga. The sample applications can be found in the folder of the Java files in test/vga. The arbiter can be found in the folder vhdl/simpcon.
[edit] Necessary Changes
[edit] Startup.java
To be able to use both the VGA and JOP it is necessary to split up the memory into two parts. This is done in the file Startup.java. The return value of the function getRamSize() has to be changed. Uncomment all code lines and return the following:
- return 640*1024/4;
As a consequence only 640 kB RAM are used for JOP and 384 kB RAM are left of the external memory for the VGA controller.
[edit] Pin Configuration of VGA Controller
- vga_h_out PIN_60 // horizontal frequency
- vga_v_out PIN_61 // vertical frequency
- vga_rgb[0] PIN_120 // colour RED low Bit
- vga_rgb[1] PIN_62 // colour RED high Bit
- vga_rgb[2] PIN_122 // colour BLUE Bit
- vga_rgb[3] PIN_121 // colour GREEN Bit
- ground
[edit] Necessary Hardware for the VGA Interface
To be able to connect the FPGA Board to a VGA, a very simple digital-to-analog converter (using resistors) was used. The maximum input voltage (maximum brightness) at the VGA signal is 0.7 V. The input resistance accounts 75 Ohm. The VCCIO of the used board is 3.3 V. Consequently the following voltage divider is used to be able to adjust 4 different intensities of each colour:
470
_____
HBit O----| |-----o
----- |
|
1k |
_____ | 470
LBit O----| |-----o _____
----- | Bit O----| |-----o
| ----- |
| |
- -
| | | |
| | 75 (video input) | | 75 (video input)
| | | |
- -
| |
| |
| |
--- ---
In the JopVga project only 4 Bit/Pixel were used. Consequently 16 different colours can be painted. Only the RED Video Signal has the four different intensities (illustrated in the left figure). For the output of the other two colours the right schematic was used.
The pinout of the VGA Connector is depicted in the following:
Pin Signal
- 1 Red Video
- 2 Green Video
- 3 Blue Video
- 4 Monitor ID - Bit 2
- 5 Ground
- 6 Red Ground
- 7 Green Ground
- 8 Blue Ground
- 9 [KEY]
- 10 Sync Ground
- 11 Monitor ID - Bit 1
- 12 Monitor ID - Bit 0
- 13 Horizontal Sync
- 14 Vertical Sync
- 15 N/C (Reserved)
[edit] Sample Application: ClockVgaLine.java
The ClockVGALine application displays a coloured display with some lines. At the start of the application the VGA memory is filled with the pixel information. To be sure that also the JOP is doing progress a Clock can be seen. A VGA display can show the pixel information that the VGA controller receives from the shared memory.
[edit] Files involved
- Top-level: jop.qsf, jop.cdf, jop.qpf
- Arbiter: sc_arbiter.vhd, sc_arbiter_pack.vhd
- VGA: dpram.vhd, vga.vhd
The dpram.vhd is Quartus Altera specific. When using a different FPGA another dual port RAM has to be used.
[edit] ToDo
I know there are still a couple of problems when using the VGA display. Regrettably I haven't had the time to figure out all the problems. In addition it would be very nice for example to implement the pipelined read access of the VGA controller. Also a small graphic library would be very useful for any kind of application. So everybody is welcome to implement the mentioned missing features and to put forth the project. ;-)
