Actel

From JopWiki

A start to port JOP to the ACTEL ProASIC FPGA.

Issues:

• Libero uses absolute path in the project file
• Libero copies the VHDL files in the project sub directory - not so nice with generated VHDL
• The starter kit does not have an RS232 interface and no RAM

Next Steps:

• Try VHDL memory files to compile
• Read the datasheet
• See how big a part of JOP (e.g. stack.vhd) is in Actel cells
• Get a blinking LED in JOP microcode
• Solder a serial interface
• Route a board with SRAM and RS232
• What about ZigBee on the add-on board?